JBD leads the transformation of the LEDoS industry: 12-inch wafer reconstruction opens a new stage of large-scale mass production

Against the backdrop of rapid penetration of AI technology into terminal products, AI/AR smart glasses are ushering in a new round of industry focus. From the Ray-Ban Meta series launched by Meta, to the release of new generation products by AR terminal manufacturers such as Rokid, RayNeo, and Even Realities, to the entry of companies from different industries such as Alibaba, Xiaomi, and Li Auto, the industry trend has become increasingly clear - AI/AR smart glasses are gradually moving from the "proof of concept" stage to "large-scale application."

Figure 1: Scene diagram of AR smart glasses

Information from Essilor Luxottica's fourth quarter 2025 financial report shows that the AI ​​smart glasses it launched in cooperation with Meta have sold more than 7 million pairs in 2025. Driven by technology giants and various forces in the industry chain, the smart glasses market is accelerating into the stage of productization and scale.

AI makes AR smart glasses a more natural, low-threshold human-computer interaction interface; and AR smart glasses provide a platform for AI that is closest to daily life scenarios. In the context of virtual and real integration gradually becoming the mainstream interaction paradigm, display technology has become the core variable that determines the upper limit of experience - it not only affects the quality of visual presentation, but is also directly related to device size, power consumption and wearing comfort.

The current development direction of micro-display technology is pointing to LEDoS solutions with the advantages of lower power consumption, higher brightness, smaller size and higher contrast. The technology is widely seen as a critical path to next-generation AR displays. However, the industrial reality is more complex: cost is still the key variable that determines whether it can truly achieve scale.

1. Cost is a key variable in the commercialization of LEDoS

In the development process of AR smart glasses, the comfort of product experience, the acceptability of price and the integrity of ecological content form the iron triangle that supports market growth. Only by continuing to expand the intersection of the three can hardware products truly respond to the expectations of the consumer market and enter the stage of scale growth.

Among the existing technology paths, LEDoS is generally regarded as the most promising solution that takes into account both performance and form design. Its advantages are reflected in multiple dimensions: extremely high brightness ensures that AR virtual images are clearly visible in complex light environments; ultra-small light engine size helps achieve thinner and lighter glasses structure design; lower power consumption provides space for the battery life of the entire machine.

However, the practical challenges are equally clear - LEDoS light engines currently account for a relatively high proportion of the overall hardware cost, which directly affects the product pricing range and market positioning, and restricts the overall industry pace to a certain extent.

When the cost of core display devices is difficult to effectively reduce, products often can only stay in high-end niche markets, making it difficult to form economies of scale to support the AR industry chain system that has just become more complete.

Therefore, cost is becoming a key variable that determines whether a technology path can truly realize its market potential. Only by breaking through the cost boundary of large-scale mass production can terminal products enter the consumer-level price range, thereby promoting AR smart terminals from the trial period to the real mass production period.

2. CMOS backplane is the key to determining the cost of LEDoS

Further dismantling the cost structure of LEDoS reveals that the key cost does not entirely come from Micro LED epitaxy, but from the CMOS (Complementary Metal Oxide Semiconductor) backplane.

CMOS backplane involves complex semiconductor processes, circuit design and expensive photomask investment, and its unit area price is much higher than that of III-V compound epitaxial wafers. At the same time, in order to meet the needs of AR near-eye displays for higher pixel density, more complex driving functions, and lower power consumption, CMOS process nodes are continuing to evolve to advanced processes below 22nm, and such advanced processes are mainly concentrated on 12-inch wafer platforms to achieve large-scale production.

This means that every 12-inch CMOS backplane carries extremely high manufacturing value. Therefore, the cost issue for LEDoS is how to maximize the effective use of this high-value 12-inch CMOS area.

During the manufacturing process, backplane utilization efficiency mainly depends on three factors: the effective pass rate of the front-end light-emitting unit, the yield performance of the integration stage, and the final available area ratio. Any addition from epitaxial defects, size mismatch, or integration losses will be amplified across the entire 12-inch backplane, creating significant cost pressure.

In other words, when 12-inch CMOS becomes the value center, the manufacturing logic must revolve around a core issue: how to minimize the waste of expensive backplane area.

Table 1: LEDoS microdisplay

3. Structural limitations of the traditional W2W path

In the traditional LEDoS integration path, Micro LED and CMOS backplane are usually integrated using wafer-to-wafer bonding (Wafer-to-Wafer, W2W). However, this path gradually exposed two structural limitations during the actual mass production process.

1. Yield related

Since the W2W solution cannot conduct effective electrical testing before bonding, manufacturers cannot know the defect area in advance, which means that the expensive CMOS backplane must passively absorb the yield loss caused by the previous process (such as defects, wavelength unevenness, etc.).

Any local epitaxial defects will cause the corresponding CMOS area to be removed together. In this model, expensive CMOS is forced to pay for the upstream defect rate.

Figure 2: Comparison of CMOS backplane utilization

2. Size mismatch leads to low utilization

Currently, Micro LED epitaxial wafer sizes are still mainly 4 inches and 6 inches, while CMOS backplanes have fully entered the 12-inch platform. The size mismatch between the two inevitably results in a large amount of unusable backplane area during the wafer-level bonding process.

For example, the utilization rate of a single 8-inch to 12-inch CMOS backplane is only 44%; when two 6-inch and 12-inch CMOS are bonded, the utilization rate is 50%; and JBD's current method integrates 7 4-inch epitaxial wafers with 12-inch CMOS, and the utilization rate can reach about 78%. Even though it is the best solution in the industry, it still does not reach the ideal level.

It is against this background that JBD judged that structural waste is continuing to weaken the value of CMOS production capacity and has become the root cause of LEDoS's difficulty in breaking through the cost bottleneck.

4. From W2W to D2W: Reconstruction of manufacturing logic

At the same time, the industry is also facing another key reality: Although CMOS backplanes have fully entered the 12-inch era, the size upgrade of light-emitting epitaxy faces obvious bottlenecks. Limited by material system differences, epitaxial uniformity control and the difficulty of large-size bonding processes, the industrialization path for 12-inch luminescent epitaxy has not yet been truly opened up. The 8-inch solution also faces potential problems such as low bonding yield. At present, Micro LED epitaxy is still mainly concentrated on 4-inch and 6-inch platforms.

This means that in the foreseeable stage, there is still a large uncertainty in the path to match 12-inch CMOS by expanding the epitaxial wafer size.

Against this background, JBD chose the wafer reconstruction path: Die-to-Carrier-to-Wafer (D2W) solution. The manufacturing process of this path changes from the traditional "wafer-to-wafer binding" to "first screening, then reconstruction, and finally integration", which can effectively isolate the impact of front-end defects on back-end integration, making CMOS The process does not passively bear unnecessary yield superposition pressure, thereby significantly improving backplane utilization and overall yield.

This transformation is not a simple process optimization, but a reconstruction of manufacturing logic.

1. Pre-screening: Stop problems before bonding

By pre-sorting the bare wafers, defective areas can be identified and eliminated before bonding, leaving only parts that are uncontaminated and suitable for subsequent processes. This process step alone can increase the effective utilization of epitaxy incoming materials from about 70% to nearly 100%, and CMOS no longer bears the loss of upstream defects.

2, 12-inch CMOS complete lamination, lossless reconstruction

The 12-inch Carrier formed through reconstruction and then fully integrated with the 12-inch CMOS can achieve nearly 100% area utilization.

When the backplane utilization approaches full area utilization, the CMOS unit cost can be more effectively spread, thereby creating room for further reductions in the cost of LEDoS microdisplays and light engines.

Figure 3: Left, 7 pieces of 4-inch epitaxial wafers; right, 12-inch silicon-based reconstructed wafers

As the cost structure continues to be optimized, not only the price of end products is expected to gradually decline, but the upstream and downstream of the industrial chain will also accelerate technological evolution due to scale expansion, thus forming a positive cycle of technological progress and cost reduction.

5. Drive the lowest cost competitiveness through technological reconstruction

In the critical stage of AR smart glasses moving towards scale, whether LEDoS can truly make a breakthrough depends not only on performance parameters, but also on whether its manufacturing system can support a large-scale cost structure.

JBD's move from 4-inch wafer-to-wafer bonding to 12-inch reconstruction process is based on a deep insight into industry trends and cost logic. By eliminating unnecessary process losses and maximizing the utilization value of CMOS backplanes, JBD has always maintained the world's lowest unit cost of LEDoS chips. This technology iteration not only marks JBD's leading position in mass production technology, but also lays a solid foundation for the commercialization and popularization of the global AR smart glasses industry.

When manufacturing logic changes, the industry curve will also turn. For the AR smart glasses market, this is not only a process architecture upgrade, but also an important turning point towards large-scale application. (Text: Emerson / TrendForce)

2025 Micro LED display and non-display application market analysis-2H25

Report language: Chinese / English

Number of report pages: 160 pages

Publication date: May 31/November 30, 2025

Research field: M microLED